1. Field of the Invention
The present invention relates to a transistor integrated circuit formed on a wafer, and particularly to a semiconductor device capable of obtaining a characteristic equivalent to a design value where an active region or a gate of a MOS transistor is a bent pattern, and a method of evaluating the semiconductor device.
2. Description of the Related Art
With the objective of speeding up a device, an SOI (Silicon On Insulator) substrate in which a thin silicon layer is formed on an insulating layer, has been in heavy usage in recent years. A method of forming a transistor on an SOI is basically similar to a process using a bulk silicon wafer.
When device isolation is carried out by a LOCOS (Local Oxidation Of Silicon) method at this time, the edges of an SOI layer provided on a buried oxide film 2 are brought to bird beaks due to a LOCOS oxide film 1 as shown in FIG. 4A. When a gate oxide film 4 is formed under such shapes and a gate 5 is formed, a parasitic transistor 7 is formed at each edge portion of an active region 3 where the gate 5 overlaps. Therefore, a transistor to be formed takes a configuration in which the parasitic transistor 7 is connected in parallel with a transistor 6 of the present device.
Since the impurity concentration of each bird beak is reduced due to ion implantation conditions, annealing in each process steps, etc., the parasitic transistor is easy to be reduced in threshold voltage as compared with the transistor of the present device. Therefore, as shown in FIG. 4B, a hump phenomenon in which humps appear, occurs in the characteristic of a drain current Id relative to a gate voltage Vg. In order to suppress the hump phenomenon, for example, ion implantation is normally effected on the bird beaks, thereby taking or carrying out countermeasures to raise a channel concentration of a parasitic transistor region and suppress the starting up or raising of the parasitic transistor.
Upon device's circuit design, a spice parameter extracted from a transistor characteristic of an evaluating TEG (Test Element Group) is used to carry out the circuit design. As shown in FIG. 3A, a transistor having simple pattern shapes in which a gate 11 and an active region 12 intersect at right angles, is used in TEG at the extraction of the parameter.
On the other hand, however, each of patterns for an active region and a gate in an actual circuit pattern cannot be configured in a simple shape like a TEG pattern. In the case of, for example, an inverter circuit or the like, it assumes a bent pattern to connect two adjacent active regions by one gate pattern.
With a view toward making a pattern layout in consideration of high integration such that elemental devices can be formed on a wafer as many as possible, such a pattern layout that a gate 13 is formed on an active region 14 having a bent shape as shown in FIG. 3B is also used.
Now, a patent document (Japanese Unexamined Patent Publication No. Hei 10(1998)-93101) has disclosed a method of providing an impurity region higher in concentration than an active region between the active region and an insulating layer to suppress a hump characteristic, thereby preventing concentration of an electric field from occurring due to etching of an insulating film at an edge portion adjacent to the active region. Further, patent documents (Japanese Unexamined Patent Publication Nos. 2002-9292 and 2003-86807) respectively have disclosed a method of performing impurity injection for suppressing turning on of a parasitic transistor on each side portion of an active region without making use of a mask using a photoresist to thereby prevent a hump characteristic.
On the other hand, when patterns for an active region having a bent shape and a gate are formed using photography, the interior of a bent portion of a photoresist's pattern do not assume the right angle as in the photomask's pattern and is curved as indicated by a portion B in FIG. 3B. When, for example, the active region is formed while maintaining the curved pattern as it is, a curved portion overlaps the gate pattern where the pattern interval between the bent active region and the gate is short. This results in the same as that a channel width became longer than a design value, and hence a transistor characteristic varies.
A section taken along line A-A of FIG. 3B is shown in FIG. 3C. An active region 14 provided on a buried oxide film 15 is isolated by a LOCOS oxide film 16, and a gate 13 is formed on a gate oxide film 17. In a transistor having an SOI structure in particular, the edge portion of an active region based on a LOCOS oxide film assumes a bird beak shape when the curved active region overlaps a gate's pattern. Therefore, a parasitic transistor region becomes wide and hence a hump phenomenon of an Id-Vg characteristic is exhibited greater.
Under such circumstances, the difference in characteristic becomes large between a transistor characteristic of an actual device and a spice parameter used in circuit design introduced from TEG so that an integrated circuit cannot obtain characteristics such as shown in circuit design. When a curved active region overlaps a gate pattern even in the case of the implantation of an impurity into an edge region, which is carried out for hump suppression where a transistor is formed in an SOI substrate, the effect of the impurity injection is not obtained and hence a hump characteristic is not improved.